David Black-Schaffer

professor vid Institutionen för informationsteknologi, Datorteknik

E-post:
david.black-schaffer[AT-tecken]it.uu.se
Telefon:
018-471 6830
Mobiltelefon:
076-8242017
Besöksadress:
Rum ITC 1240 ITC, Lägerhyddsvägen 2, hus 1
752 37 UPPSALA
Postadress:
Box 337
751 05 UPPSALA

Kort presentation

I investigate modeling and measuring the effects of shared memory resources (caches and off-chip bandwidth) in multicore processors on power and performance. My work addresses both theoretical models and techniques for measuring actual behavior on real systems. Currently I am applying these techniques to improve task scheduling on heterogeneous systems, to predict power and performance, and to develop smart memory systems.

Research / Uppsala Architecture Research Team

Nyckelord: computer architecture memory systems simulation runtimes scheduling

Mina kurser

Biografi

I received my PhD in Electrical Engineering from Stanford University in 2008. My research was in programming for real-time embedded processing on many-core processors in the Concurrent VLSI Architecture Group working with William Dally. After my PhD I worked at Apple on the development of the first OpenCL implementation for heterogeneous parallel processing across CPUs and GPUs, and then as a postdoc researcher in computer architecture in the Dept. of Information Technology at Uppsala University. I was appointed assistant professor in 2010 in the architecture research group at Uppsala looking at parallel programming systems and optimizations as part of the UPMARC research project. In 2014 I was promoted to associate professor (docent, lektor).

In addition to research, I lead the ScalableLearning project to bring the benefits of active, flipped-classroom teaching to thousands of students in Sweden and abroad.

Google Scholar Citations

Grants and Awards

Teaching

Presentations

Forskning

My research focuses on improving efficiency in computers by making the memory system more intelligent. Our work includes more clever ways of moving and placing data in the memory system, integrating data movement with the processor core itself, adapting runtime schedules for better data movement, and the analysis and modeling of data movement.

Publikationer

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